Power, Speed and Density Trade-offs in Modern FPGA Architectures: A Review for Optimization Techniques

Keywords: Field Programmable Gate Arrays (FPGAs), Programmable logic blocks, Programmable routing, I/O blocks, Look-up-Table (LUT), Power Consumption
Engr.Dilip kumar.A.Ramnani - Department of Electronic Engineering, Dawood University of Engneering & Technology Karachi, Pakistan
Dr.Khalil ur Rehman Dayo - Department of Electronic Engineering, Mehran University of Engineering &Technology Jamshoro, Pakistan
Dr. Muhammad Amir - Department of Electronic Engineering, Sir Syed University of Engineering & Technology Karachi, Pakistan
Published Date: 2019-04-03

FPGAs are an arrangement of gates that can be reprogrammed or reconfigured. In FPGA, Logic functions are usually implemented by Logic Blocks, Programmable Routing, and Input-output Blocks. FPGAs are more adaptable than ASICs but they are relatively larger in size, slower and consume more power because of routing which uses almost 90% of the overall area in FPGA. Our work explains detailed analysis of the existing techniques addressing different issues such as; routing, mapping, cluster, optimization, and energy efficiency related to FPGA power, speed delay and area density. By analyzing different FPGAs architecture techniques, we revealed that low power consumption and fast speed can be achieved by designing FPGA with large cluster size, however efficient area can be achieved by designing FPGA with small cluster size. Lookup table with four input gives most effective tradeoff between Power, speed and Area. This paper also suggests the latest area for optimizing the power, speed delay and area density for different FPGA architecture.

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